1. Field of the Invention
This invention relates generally to memory arrays and, more specifically, to a voltage regulator and booster circuit for reading memory cells of a memory array at supply voltages lower than the actual erased threshold voltage of the memory array.
2. Description of the Prior Art
Memory devices are fabricated using semiconductor process technology. As line widths are reduced in progression of the process technology, it may be desirable not only to design and fabricate entirely new versions of the products, but to "shrink" or scale existing products to smaller sizes with the new technology. This requires a review and analysis of the design and architecture of the product and the manner in which the attempted scaling of its size may adversely affect its operation.
In general, in order to read the data of a memory cell in a memory array, a measurement of the threshold voltage of the memory element is required. The memory cell is said to be erased if the threshold voltage of the memory cell is low, and to be programmed if the threshold voltage is high. The cell is read by applying a voltage to the control gate of a transistor comprising the memory cell. If the applied voltage is higher than the threshold voltage, current flows through the memory cell if it is erased, if no current flows, the memory cell is programmed. The programming margin of the memory cell is the voltage difference between the maximum applied control gate voltage and the programmed threshold voltage of the programmed memory cell. A programmed memory cell will not conduct current when read by application of a control gate voltage of a lower magnitude than the high threshold voltage of the memory cell.
In most implementations, the control gate voltage used to read the memory array is the supply voltage of the system. If the programmed threshold voltage of the memory cell is lower than the maximum value of the supply voltage, a programmed memory cell cannot be detected using the classic technique.
Scaling memory devices to smaller sizes has the effect of reducing the voltage range at which the memory devices operate. When a memory device is shrunk, the programmed threshold voltage of the memory cell is decreased and the effective programming margin is lowered. Furthermore, a smaller memory cell typically dictates a lower read current. The present invention arose from the necessity to scale a memory device (Erasable Programmable Read Only Memory (EPROM) semiconductor device) to a small geometry manufacturing process. The operating voltage for the semiconductor device being produced on the new manufacturing process is greater than the programming margin of a programmed memory cell of the memory device. Thus, the memory cells cannot be read with a full supply voltage because it will be read incorrectly.
One way to read memory cells at supply voltage levels lower than the actual threshold voltage of the memory array is to use a ring oscillator and a charge pump. The ring oscillator is an RC clock that generates a clock signal that pumps the row voltage greater than the supply voltage V.sub.DD. The problem with using this approach is that the ring oscillator is only good for one voltage. Furthermore, this approach burns a lot of current. This is due to the fact that the ring oscillator is always pumping the row voltage higher each cycle. This causes further problems especially if the supply voltage is raised higher. If the supply voltage is raised higher, the ring oscillator may no longer be required to raise the row voltage of the memory array. In fact, if the ring oscillator continues to run, the row voltage may be raised to a voltage level that is too high. Since the memory cell of the memory array cannot be read with a full supply voltage, the memory cell will be read incorrectly.
Therefore a need existed to provide a voltage regulator and booster circuit for use with a memory array. The voltage regulator and booster circuit will allow the reading of memory cells in a memory array at voltage levels lower than the actual threshold voltage of the memory array. The voltage regulator and booster circuit will further allow a memory cell in the memory array to be read correctly even if the supply voltage V.sub.DD to the memory device may be at a level above the programmed margin of the memory cell. The voltage regulator and booster circuit is able to clamp the row voltage of a memory array at a value which is greater than an unprogrammed threshold voltage level of the memory cell and less than a programmed threshold voltage level of the memory cell thereby allowing reading of the memory cell at higher voltage levels. The voltage regulator and booster circuit must further be able to determine if the system is operating in a high voltage mode or a low voltage mode with a minimal amount of circuitry. The voltage regulator and booster circuit must also be able to automatically boost the row voltage of the memory array in the low voltage mode and shunt increases in row voltage levels to ground in a high voltage mode.